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| CY8CTST110 TrueTouchTM Single-Touch Touchscreen Controller Features TrueTouchTM Capacitive Touchscreen Controller Supports Single-Touch Touchscreen Applications Supports up to 24 X/Y Sensor Inputs Supports Screen Sizes 4.3" and Below (Typical) Fast Scan Rates: Typical 0.5 ms per Sensor High Resolution: Typical 320 x 240 for 2.6" Screen Available in 32-Pin QFN Package Transition to Higher Function Multi-Touch Gesture Device Highly Configurable Sensing Circuitry Allows Maximum Design Flexibility Allows Trade-Off Between Scan Time and Noise Performance Provides Maximum EMI Immunity Selectable Spread-Spectrum Clock Source Low Power TrueTouch Single-Touch Touchscreen Device 4 mA Average Supply Current at 8 ms Report Rate 2 mA Average Supply Current at 16 ms Report Rate Powerful Harvard Architecture Processor M8C Processor Speeds to 24 MHz Low Power at High Speed 2.7V to 5.25V Operating Voltage Industrial Temperature Range: -40C to +85C Flexible On-Chip Memory 8K Flash Program Storage, 50000 Erase/Write Cycles 512 Bytes SRAM Data Storage In-System Serial Programming (ISSPTM) Partial Flash Updates Flexible Protection Modes EEPROM Emulation in Flash Complete Development Tools Free Development Software (PSoC DesignerTM) TrueTouch Touchscreen Tuner Full-Featured, In-Circuit Emulator and Programmer Full Speed Emulation Complex Breakpoint Structure 128K Trace Memory Precision, Programmable Clocking Internal 2.5% 24/48 MHz Oscillator Internal Oscillator for Watchdog and Sleep Programmable Pin Configurations 25 mA Sink, 10 mA Drive on All GPIO Pull Up, Pull Down, High Z, Strong, or Open Drain Drive Modes on All GPIO Up to 8 Analog Inputs on GPIO Configurable Interrupt on All GPIO Additional System Resources 2 I CTM Master, Slave, and Multi-Master to 400 kHz Watchdog and Sleep Timers User-Configurable Low Voltage Detection Integrated Supervisory Circuit On-Chip Precision Voltage Reference Logic Block Diagram Cypress Semiconductor Corporation Document Number: 001-46931 Rev. *B * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised July 28, 2008 [+] Feedback CY8CTST110 TrueTouch Functional Overview The TrueTouch family provides the fastest and most efficient way to develop and tune a capacitive touchscreen application. A TrueTouch device includes the configurable TrueTouch block, configurable analog and digital logic, and programmable interconnect. This architecture enables the user to create flexible, customized touchscreen configurations to match the requirements of each individual touchscreen application. Various configurations of Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts. The TrueTouch architecture consists of four main areas: the Core, the System Resources, the Digital System, and the TrueTouch Analog System. Configurable global bus resources allow combining all the device resources into a complete custom touchscreen system. Each CY8CTST110 TrueTouch device includes four digital blocks and the TrueTouch controller block that provides single-touch sensing and scanning control circuitry for touchscreen applications. The CY8CTST110 is offered in a 32-pin QFN package with up to 28 general purpose IO (GPIO), and support of up to 24 X/Y sensors. When designing touchscreen applications, refer to the UM data sheet for performance requirements to meet and detailed design process explanation. The Digital System The Digital System consists of four digital PSoC blocks. Each block is an 8-bit resource that is used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Digital peripheral configurations include the following. PWMs (8 to 32 bit) PWMs with dead band (8 to 32 bit) Counters (8 to 32 bit) Timers (8 to 32 bit) UART 8 bit with selectable parity SPI master and slave I2C slave and multi-master Pseudo random sequence generators (8 to 32 bit) The digital blocks are connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow signal multiplexing and performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by TrueTouch device family. This allows the optimum choice of system resources for your application. Family characteristics are shown in Table 1 on page 4. Figure 1. Digital System Block Diagram Port 3 Port 2 Port 1 Port 0 The TrueTouch Core The Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO (Internal Main Oscillator) and ILO (Internal Low speed Oscillator). The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a four MIPS 8-bit Harvard architecture microprocessor. System Resources provide the following additional capabilities: Digital clocks to increase the flexibility of the PSoC mixed-signal arrays. I2C functionality to implement an I2C master and slave. An internal voltage reference, MultiMaster, that provides an absolute value of 1.3V to a number of TrueTouch subsystems. Digital Clocks FromCore To System Bus ToAnalog System DIGITAL SYSTEM Digital PSoC Block Array Row 0 DBB00 DBB01 DCB02 The Digital System consists of an array of digital blocks that may be configured into any number of digital peripherals. The digital blocks are connected to the GPIO through a series of global buses that can route any signal to any pin, freeing designs from the constraints of a fixed peripheral controller. The Analog System consists of four analog PSoC blocks, supporting comparators and analog-to-digital conversion up to 8 bits in precision. Implementation of touchscreen applications allow additional digital and analog resources to be used, depending on the touchscreen design. Row Input Configuration Various system resets supported by the M8C. 4 DCB03 4 Row Output Configuration 8 8 8 8 GIE[7:0] GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0] Document Number: 001-46931 Rev. *B Page 2 of 32 [+] Feedback CY8CTST110 The Analog System The Analog System consists of four configurable blocks that allow the creation of complex analog signal flows. Implementation of touchscreen applications allow additional analog resources to be used, depending on the touchscreen design. Analog peripherals are very flexible and may be customized to support specific application requirements. Some of the additional TrueTouch analog functions for this device (most available as user modules) are: The Analog Multiplexer System The Analog Mux Bus connects to every GPIO pin. Pins are connected to the bus individually or in any combination. The bus also connects to the analog system for capacitive sensing with the TrueTouch block comparator. An additional 8:1 analog input multiplexer provides a second path to bring Port 0 pins to the analog array. Switch control logic enables selected pins to switch dynamically under hardware control. This allows capacitive measurement for touchscreen applications. Other multiplexer applications include: Analog-to-digital converters (single or dual, with 8-bit resolution) Pin-to-pin comparator Single-ended comparators (up to 2) with absolute (1.3V) reference or 8-bit DAC reference 1.3V reference (as a System Resource) Chip-wide mux that allows analog input from any IO pin. Electrical connection between any IO pin combinations. Additional System Resources System Resources, some of which are listed in the previous sections, provide additional capability useful to complete systems. Additional resources include low voltage detection and power on reset. Brief statements describing the merits of each system resource follow. Figure 2. Analog System Block Diagram Array Input Configuration Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks may be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.3 voltage reference provides an absolute reference for the analog system, including ADCs and DACs. Versatile analog multiplexer system. ACI0[1:0] A IO ll X X X X ACI1[1:0] ACOL1MUX Analog MuxBus X Array ACE00 ASE10 ACE01 ASE11 Document Number: 001-46931 Rev. *B Page 3 of 32 [+] Feedback CY8CTST110 Getting Started To understand the TrueTouch silicon, read this data sheet and use the PSoC DesignerTM Integrated Development Environment (IDE). This data sheet is an overview of the general silicon information and electrical specifications. For in depth touchscreen application information, including touchscreen specific specifications, read the touchscreen user module data sheet that is supported by this specific device. Development Kits Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store contains development kits, C compilers, and all accessories for PSoC development. Go to the Cypress Online Store web site at http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page and click PSoC (Programmable System-on-Chip) to view a current list of available items. TrueTouch Device Characteristics Depending on your TrueTouch device selected for a touchscreen application, characteristics and capabilities of each device change. Table 1 lists the touchscreen sensing capabilities available for specific TrueTouch devices. The TrueTouch device covered by this data sheet is highlighted in this table. Table 1. TrueTouch Device Characteristics Current Consumption[2] Scan Speed (ms)[1] Single-Touch Max Screen Size (Inches) Multi-Touch Gesture Multi-Touch All-Point Flash Size Technical Training Modules Free PSoC technical training modules are available for users new to PSoC. Training modules cover designing, debugging, advanced analog, and general PSoC related topics. Go to http://www.cypress.com/training. Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to http://www.cypress.com, click on Design Support located on the left side of the web page, and select CYPros Consultants. Sensor Inputs TrueTouch Part Number SRAM Size Technical Support 512 Bytes CY8CTST110 CY8CTST120 CY8CTMG110 CY8CTMG120 CY8CTMA120 up to 4.3" Y 24 up to 8.4" Y 44 up to 4.3" Y 24 up to 8.4 44 Y N N Y Y Y N N N N Y 0.5 0.5 0.5 0.5 3 16 3 16 8K 16K 1K 8K 512 Bytes PSoC application engineers take pride in fast and accurate response. They are available with a four hour guaranteed response at http://www.cypress.com/support. Application Notes A long list of application notes can assist you in every aspect of your design effort. To view the PSoC application notes, go to http://www.cypress.com web site and select Application Notes under the Design Resources list located in the center of the web page. Application notes are sorted by date by default. 16K 1K 16K 1K up to 7.3" Y 37 0.12 16 Development Tools PSoC Designer is a Microsoft(R) Windows based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE and application runs on Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP (see Figure 3 on page 5). PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the PSoC, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs. PSoC Designer also supports a high level C language compiler developed specifically for the devices in the family. Notes 1. Per Sensor typical. Depends on touchscreen panel. For MA120 per X/Y crossing Vcc = 3.3V 2. Average mA supply current. Based on 8 ms report rate, except for MA120. Document Number: 001-46931 Rev. *B Page 4 of 32 [+] Feedback CY8CTST110 Figure 3. PSoC Designer Subsystems 300-baud modem, LIN Bus master and slave, fan controller, and magnetic card reader. Context Sensitive Help PSoC Designer Graphical Designer Interface Application Editor The Application Editor edits C language and Assembly language source code. It also assembles, compiles, links, and builds. Assembler. The macro assembler allows the seamless merging of the assembly code with C code. The link libraries automatically use absolute addressing or are compiled in relative mode and linked with other software modules to get absolute addressing. Commands Results Importable Design Database Device Database Application Database Project Database User Modules Library PSoC Configuration Sheet PSoC Designer Core Engine C Language Compiler. A C language compiler that supports the PSoC family of devices is available. Even if you have never worked in the C language before, the product quickly helps you create complete C programs for the PSoC family devices. The embedded, optimizing C compiler provides all the features of C tailored to the PSoC architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read the program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. Manufacturing Information File Emulation Pod In-Circuit Emulator Device Programmer TrueTouch Designer Software Subsystems Device Editor The device editor subsystem enables the user to select different onboard analog and digital components called user modules using the PSoC blocks. Examples of user modules are ADCs, DACs, amplifiers, and filters. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration allows changing configurations at run time. PSoC DesignerTM sets up power on initialization tables for selected PSoC block configurations and creates source code for an application framework. The framework contains software to operate the selected components. If the project uses more than one operating configuration, then it contains routines to switch between different sets of PSoC block configurations at run time. PSoC Designer prints out a configuration sheet for a given project configuration for use during application programming in conjunction with the device data sheet. After the framework is generated, the user adds application-specific code to flesh out the framework. It is also possible to change the selected components and regenerate the framework. Design Browser The Design Browser enables users to select and import preconfigured designs into the user's project. Users can easily browse a catalog of preconfigured designs to facilitate time-to-design. Examples provided in the tools include a Hardware Tools In-Circuit Emulator A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. TrueTouch Touchscreen Tuner The TrueTouch tuner is a Microsoft(R) Windows based graphical user interface allowing developers to set critical parameters and observe changes to the touchscreen application in real time. Optimal configuration from the tuner can be immediately applied to the TrueTouch user module settings. Document Number: 001-46931 Rev. *B Page 5 of 32 [+] Feedback CY8CTST110 Designing with User Modules The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. Each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses and to the IO pins. Iterative development cycles permit you to adapt the hardware and software. This substantially lowers the risk of having to select a different part to meet the final design requirements. To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of pre-built, pre-tested hardware peripheral functions, called "User Modules." User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. The standard User Module library contains over 50 common peripherals such as ADCs, DACs timers, counters, UARTs, and other uncommon peripherals, such as DTMF generators and Bi-Quad analog filter sections. Each user module establishes the basic register settings that implement the selected function. It also provides parameters that allow you to tailor its precise configuration to your particular application. For example, a Pulse Width Modulator User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. User modules also provide tested software to cut your development time. The user module application programming interface (API) provides high-level functions to control and respond to hardware events at run time. The API also provides optional interrupt service routines that you can adapt as needed. The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE. These data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module. The development process starts when you open a new project and bring up the Device Editor, a graphical user interface (GUI) for configuring the hardware. You can pick the user modules you need for your project and map them onto the PSoC blocks with point-and-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this stage, you must also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. When you are ready to test the hardware configuration or move on to developing code for the project, perform the "Generate Application" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the high-level user module API functions. Figure 4. User Module and Source Code Development Flows Device Editor User Module Selection Placement and Parameter -ization Source Code Generator Generate Application Application Editor Project Manager Source Code Editor Build Manager Build All Debugger Interface to ICE Storage Inspector Event & Breakpoint Manager The next step is to write your main program, and any sub-routines using PSoC Designer's Application Editor subsystem. The Application Editor includes a Project Manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor provides syntax coloring and advanced edit features for both C and assembly language. File search capabilities include simple string searches and recursive "grep-style" patterns. A single mouse click invokes the Build Manager. It employs a professional-strength "makefile" system to automatically analyze all file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies used by the compiler and linker. Syntax errors are displayed in a console window. Double clicking the error message takes you directly to the offending line of source code. When all is correct, the linker builds a HEX file image suitable for programming. The last step in the development process takes place inside the PSoC Designer's Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and enables you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals. Document Number: 001-46931 Rev. *B Page 6 of 32 [+] Feedback CY8CTST110 Document Conventions Acronyms Used The following table lists the acronyms that are used in this document. Table 2. Acronyms Used Acronym AC ADC API CPU CT DAC DC ECO EEPROM FSR GPIO GUI HBM ICE ILO IMO IO IPOR LSb LVD MSb PC PLL POR PPOR PSoC(R) PWM SC SLIMO SMP SRAM Description alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current external crystal oscillator electrically erasable programmable read-only memory full scale range general purpose IO graphical user interface human body model in-circuit emulator internal low speed oscillator internal main oscillator input/output imprecise power on reset least-significant bit low voltage detect most-significant bit program counter phase-locked loop power on reset precision power on reset Programmable System-on-ChipTM pulse width modulator switched capacitor slow IMO switch mode pump static random access memory Units of Measure A units of measure table is located in the Electrical Specifications section. Table 5 on page 12 lists all the abbreviations used to measure the PSoC devices. Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexadecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (for example, 01010100b' or `01000011b'). Numbers not indicated by an `h', `b', or 0x are decimal. Document Number: 001-46931 Rev. *B Page 7 of 32 [+] Feedback CY8CTST110 Pin Information The CY8CTST110 TrueTouch device is available in a 32-Pin QFN package which is listed in the following tables. Every port pin (labeled with a "P") is capable of Digital IO and connection to the common analog bus. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO. 32-Pin Part Pinout Figure 5. CY8CTST110 32-Pin Sawn TrueTouch Device Vss P0[3], A, I, M P0[7], A, I, M Vdd P0[6], A, I, M 28 27 P0[4], A, I, M 26 P0[5], A, I, M P0[2], A, I, M 25 31 32 A, I, M, M, M, M, M, M, M, M, 12C SCL, P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] P3[1] P1[7] 30 29 1 2 3 4 5 6 7 8 9 10 M, P1[3] QFN (Top View ) 13 14 15 11 M, 12C SCL, P1[1] 12 M, P1[2] Document Number: 001-46931 Rev. *B M, 12C SDA, P1[5] M, 12C SDA, P1[0] M, EXTCLK, P1[4] M, P1[6] Vss 16 24 23 22 21 20 19 18 17 P0[0], A, I, M P2[6], M P2[4], M P2[2], M P2[0], M P3[2], M P3[0], M XRES Page 8 of 32 [+] Feedback CY8CTST110 Table 3. Pin Definitions - CY8CTST110 32-Pin (QFN) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 EP Digital IO IO IO IO IO IO IO IO IO IO IO Power IO IO IO IO Input IO IO IO IO IO IO IO IO IO IO Power IO IO IO Power Power Type Analog I, M M M M M M M M M M M M M M M M M M M M M I, M I, M I, M I, M I, M I, M I, M Name P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] P3[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES P3[0] P3[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd P0[7] P0[5] P0[3] Vss Vss Description Analog column mux input, integrating input. I2C Serial Clock (SCL). I2C Serial Data (SDA). I2C Serial Clock (SCL), ISSP-SCLK[3]. Ground. Connect to circuit ground. I2C Serial Data (SDA), ISSP-SDATA[3]. Optional External Clock Input (EXTCLK). Active high external reset with internal pull down. Analog column mux input. Analog column mux input. Analog column mux input. Analog column mux input. Supply voltage. Bypass to ground with 0.1 uF capacitor. Analog column mux input. Analog column mux input. Analog column mux input, integrating input. Ground. Connect to circuit ground. Exposed pad is internally connected to ground. Connect to circuit ground. LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input. Note 3. These are the ISSP pins, which are not High Z at POR (Power On Reset) Document Number: 001-46931 Rev. *B Page 9 of 32 [+] Feedback CY8CTST110 56-Pin Part Pinout The 56-pin SSOP part is for the CY8CTST110 On-Chip Debug (OCD) TrueTouch device. Note This part is only used for in-circuit debugging. It is NOT available for production. Figure 6. CY8CTST110 56-Pin TrueTouch Device Vss AI, P0[7] AI, P0[5] AI, P0[3] AI, P0[1] P2[7] P2[5] P2[3] P2[1] NC NC NC NC OCDE OCDO SMP Vss Vss P3[3] P3[1] NC NC I2C SCL, P1[7] I2C SDA, P1[5] NC P1[3] SCLK, I2C SCL, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 Vdd P0[6], AI P0[4], AI P0[2], AI P0[0], AI P2[6] P2[4] P2[2] P2[0] NC NC P3[2] P3[0] CCLK HCLK XRES NC NC NC NC NC NC P1[6] P1[4], EXTCLK P1[2] P1[0], I2C SDA, SDATA NC NC SSOP Table 4. Pin Definitions - CY8CTST110 56-Pin (SSOP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Type Digital Power IO IO IO IO IO IO IO IO Analog I I I I Pin Name Vss P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] NC NC NC NC OCDE OCDO SMP Vss Vss P3[3] Description Ground. Connect to circuit ground. Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. I I OCD OCD Power Power Power IO Direct switched capacitor block input. Direct switched capacitor block input. No connection. Leave Floating. No connection. Leave Floating. No connection. Leave Floating. No connection. Leave Floating. OCD even data IO. OCD odd data output. Switch Mode Pump (SMP) connection to required external components. Ground. Connect to circuit ground. Ground. Connect to circuit ground. Document Number: 001-46931 Rev. *B Page 10 of 32 [+] Feedback CY8CTST110 Table 4. Pin Definitions - CY8CTST110 56-Pin (SSOP) (continued) Pin No. 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 IO Type Digital Analog Pin Name P3[1] NC NC P1[7] P1[5] NC P1[3] P1[1] Vss NC NC P1[0] P1[2] P1[4] P1[6] NC NC NC NC NC NC XRES HCLK CCLK P3[0] P3[2] NC NC P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd Description IO IO IO IO Power No connection. Leave Floating. No connection. Leave Floating. I2C Serial Clock (SCL). I2C Serial Data (SDA). No connection. Leave Floating. Crystal Input (XTALin), I2C Serial Clock (SCL), ISSP-SCLK[3]. Ground. Connect to circuit ground. No connection. Leave Floating. No connection. Leave Floating. Crystal Output (XTALout), I2C Serial Data (SDA), ISSP-SDATA[3]. Optional External Clock Input (EXTCLK). No connection. Leave Floating. No connection. Leave Floating. No connection. Leave Floating. No connection. Leave Floating. No connection. Leave Floating. No connection. Leave Floating. Active high external reset with internal pull down. OCD high-speed clock output. OCD CPU clock output. IO IO IO IO Input OCD OCD IO IO No connection. Leave Floating. No connection. Leave Floating. IO IO IO IO IO IO IO IO Power I I I I I I Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage. Bypass with 0.1 uF capacitor to ground. LEGEND: A = Analog, I = Input, O = Output, and OCD = On-Chip Debug. Document Number: 001-46931 Rev. *B Page 11 of 32 [+] Feedback CY8CTST110 Electrical Specifications This section presents the DC and AC electrical specifications of the CY8CTST110 TrueTouch device. For up to date electrical specifications, visit the web site http://www.cypress.com/psoc. Specifications are valid for -40oC TA 85oC and TJ 100oC as specified, except where noted. Refer Table 19 on page 20 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode. Figure 7. Voltage versus CPU Frequency 5.25 5.25 Figure 8. IMO Frequency Trim Options SLIMO Mode=1 4.75 Vdd Voltage 4.75 Vdd Voltage SLIMO Mode = 0 SLIMO Mode=0 lid g Va ratin n pe io O Reg 3.60 3.00 2.40 93 kHz 3 MHz 12 MHz CPU Frequency 24 MHz 3.00 SLIMO SLIMO Mode=1 Mode=0 SLIMO SLIMO Mode=1 Mode=1 93 kHz 6 MHz 12 MHz 24 MHz 2.40 IMOFrequency Table 5 lists the units of measure that are used in this section. Table 5. Units of Measure Symbol oC dB fF Hz KB Kbit kHz k MHz M A F H s V Vrms Unit of Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square Symbol W mA ms mV nA ns nV pA pF pp ppm ps sps s V Unit of Measure microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts Document Number: 001-46931 Rev. *B Page 12 of 32 [+] Feedback CY8CTST110 Absolute Maximum Ratings Table 6. Absolute Maximum Ratings Symbol Description TSTG Storage Temperature Min -55 Typ 25 Max +100 o Units C Notes Higher storage temperatures reduce data retention time. Recommended storage temperature is +25 oC 25 oC. Extended duration storage temperatures above 65 oC degrade reliability. TA Vdd VIO VIOZ IMIO ESD LU Ambient Temperature with Power Applied Supply Voltage on Vdd Relative to Vss DC Input Voltage DC Voltage Applied to Tri-state Maximum Current into any Port Pin Electro Static Discharge Voltage[4] Latch Up Current -40 -0.5 Vss - 0.5 Vss - 0.5 -25 2000 - - - - - - - - +85 +6.0 Vdd + 0.5 Vdd + 0.5 +50 - 200 o C V V V mA V mA Human Body Model ESD. Operating Temperature Table 7. Operating Temperature Symbol Description TA Ambient Temperature[5] TJ Junction Temperature Min -40 -40 Typ - - Max +85 +100 Units oC oC Notes The temperature rise from ambient to junction is package specific. See Table 34 on page 29. The user must limit the power consumption to comply with this requirement. Notes 4. See the user module data sheet for touchscreen application related ESD testing. 5. See the user module data sheet for touchscreen application related temperature testing Document Number: 001-46931 Rev. *B Page 13 of 32 [+] Feedback CY8CTST110 DC Electrical Characteristics The below electrical characteristics are for proper CPU core and IO operation. For capacitive touchscreen electrical characteristics, refer to the touchscreen user module data sheet. DC Chip-Level Specifications Table 8 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.7V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C. These are for design guidance only. Table 8. DC Chip-Level Specifications Symbol Vdd IDD Supply Voltage Supply Current, IMO = 24 MHz Description Min 2.40 - Typ - 3 Max 5.25 4 Units V mA Notes See Table 17 on page 18. Conditions are Vdd = 5.0V, TA = 25oC, CPU = 3 MHz, 48 MHz disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz. Conditions are Vdd = 3.3V, TA = 25oC, CPU = 3 MHz, clock doubler disabled. VC1 = 375 kHz, VC2 = 23.4 kHz, VC3 = 0.091 kHz. Conditions are Vdd = 2.55V, TA = 25oC, CPU = 3 MHz, clock doubler disabled. VC1 = 375 kHz, VC2 = 23.4 kHz, VC3 = 0.091 kHz. Vdd = 2.55V, 0oC TA 40oC. Vdd = 3.3V, -40oC TA 85oC. Trimmed for appropriate Vdd. Vdd = 3.0V to 5.25V. Trimmed for appropriate Vdd. Vdd = 2.4V to 3.0V. IDD3 Supply Current, IMO = 6 MHz using SLIMO mode. - 1.2 2 mA IDD27 Supply Current, IMO = 6 MHz using SLIMO mode. - 1.1 1.5 mA ISB27 Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. Mid temperature range. Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. Reference Voltage (Bandgap) Reference Voltage (Bandgap) Analog Ground - 2.6 4. A ISB VREF VREF27 AGND - 1.28 1.16 VREF - 0.003 2.8 1.30 1.30 VREF 5 1.32 1.33 VREF + 0.003 A V V V Document Number: 001-46931 Rev. *B Page 14 of 32 [+] Feedback CY8CTST110 DC General Purpose IO Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C. These are for design guidance only. Table 9. 5V and 3.3V DC GPIO Specifications Symbol RPU RPD VOH Description Pull Up Resistor Pull Down Resistor High Output Level Min 4 4 Vdd - 1.0 Typ 5.6 5.6 - Max 8 8 - Units k k V IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). Vdd = 3.0 to 5.25. Vdd = 3.0 to 5.25. Gross tested to 1 A. Package and pin dependent. Temp = 25 oC. Package and pin dependent. Temp = 25 oC. Notes VOL Low Output Level - - 0.75 V VIL VIH VH IIL CIN COUT Input Low Level Input High Level Input Hysteresis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output - 2.1 - - - - - - 60 1 3.5 3.5 0.8 - - 10 10 V V mV nA pF pF Table 10. 2.7V DC GPIO Specifications Symbol RPU RPD VOH Pull Up Resistor Pull Down Resistor High Output Level Description Min 4 4 Vdd - 0.4 Typ 5.6 5.6 - Max 8 8 - Units k k V IOH = 2.5 mA (6.25 Typ), Vdd = 2.4 to 3.0V (16 mA maximum, 50 mA Typ combined IOH budget). IOL = 10 mA, Vdd = 2.4 to 3.0V (90 mA maximum combined IOL budget). Vdd = 2.4 to 3.0. Vdd = 2.4 to 3.0. Gross tested to 1 A. Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC. Notes VOL VIL VIH VH IIL CIN COUT Low Output Level Input Low Level Input High Level Input Hysteresis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output - - 2.0 - - - - - - - 90 1 3.5 3.5 0.75 0.75 - - - 10 10 V V V mV nA pF pF Document Number: 001-46931 Rev. *B Page 15 of 32 [+] Feedback CY8CTST110 DC Operational Amplifier Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C. These are for design guidance only. Table 11. 5V DC Operational Amplifier Specifications Symbol VOSOA IEBOA[6] CINOA VCMOA GOLOA ISOA Description Input Offset Voltage (Absolute Value) Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range Open Loop Gain Amplifier Supply Current Min - - - - 0.0 - - Typ 2.5 10 200 4.5 - 80 10 Max 15 - - 9.5 Vdd - 1 - 30 Units mV V/oC pA pF V dB A Gross tested to 1 A. Package and pin dependent. Temp = 25 oC. Notes TCVOSOA Average Input Offset Voltage Drift Table 12. 3.3V DC Operational Amplifier Specifications Symbol VOSOA IEBOA [6] Description Input Offset Voltage (Absolute Value) Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range Open Loop Gain Amplifier Supply Current Min - - - - 0 - - Typ 2.5 10 200 4.5 - 80 10 Max 15 - - 9.5 Vdd - 1 - 30 Units mV V/oC pA pF V dB A Notes TCVOSOA Average Input Offset Voltage Drift CINOA VCMOA GOLOA ISOA Gross tested to 1 A. Package and pin dependent. Temp = 25 oC. Table 13. 2.7V DC Operational Amplifier Specifications Symbol VOSOA IEBOA[6] CINOA VCMOA GOLOA ISOA Description Input Offset Voltage (Absolute Value) Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range Open Loop Gain Amplifier Supply Current Min - - - - 0 - - Typ 2.5 10 200 4.5 - 80 10 Max 15 - - 9.5 Vdd - 1 - 30 Units mV V/oC pA pF V dB A Gross tested to 1 A. Package and pin dependent. Temp = 25 oC. Notes TCVOSOA Average Input Offset Voltage Drift Note 6. Atypical behavior: IEBOA of Port 0 pin 0 is below 1 nA at 25 C; 50 nA over temperature. Use Port 0 pins 1 to 7 for the lowest leakage of 200 nA. Document Number: 001-46931 Rev. *B Page 16 of 32 [+] Feedback CY8CTST110 DC Low Power Comparator Specifications Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V at 25C. These are for design guidance only. Table 14. DC Low Power Comparator Specifications Symbol Description VREFLPC Low Power Comparator (LPC) Reference Voltage Range ISLPC LPC Supply Current VOSLPC LPC Voltage Offset DC Analog Mux Bus Specifications Table 15 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C. These are for design guidance only. Table 15. DC Analog Mux Bus Specifications Symbol RSW RVDD Description Switch Resistance to Common Analog Bus Resistance of Initialization Switch to Vdd Min - - Typ - - Max 400 800 800 Units W W W Notes Vdd 2.7V 2.4V Vdd 2.7V Min 0.2 - - Typ - 10 2.5 Max Vdd - 1 40 30 Units V A mV Notes DC IDAC Resolution Table 16 lists IDAC typical resolution. Typical parameters apply to 5V at 25C. These are for design guidance only. Table 16. DC IDAC Resolution Symbol IDAC Description Current Output of 1 LSB (1x Setting) Min Typ 90 Max Units nA Notes Document Number: 001-46931 Rev. *B Page 17 of 32 [+] Feedback CY8CTST110 DC POR and LVD Specifications TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C. These are for design guidance only. Table 17. DC POR and LVD Specifications Symbol VPPOR0 VPPOR1 VPPOR2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VPUMP0 VPUMP1 VPUMP2 VPUMP3 VPUMP4 VPUMP5 VPUMP6 VPUMP7 Description Vdd Value for PPOR Trip PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Vdd Value for PUMP Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Min Typ 2.36 2.82 4.55 2.45 2.92 3.02 3.13 4.48 4.64 4.73 4.81 2.55 3.02 3.10 3.25 4.64 4.73 4.82 5.00 Max 2.40 2.95 4.70 2.51[7] 2.99[8] 3.09 3.20 4.55 4.75 4.83 4.95 2.62[9] 3.09 3.16 3.32[10] 4.74 4.83 4.92 5.12 Units V V V V V V V V V V V V V V V V V V V Notes Vdd must be greater than or equal to 2.5V during startup, reset from the XRES pin, or reset from Watchdog. Table 17 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C - 2.40 2.85 2.95 3.06 4.37 4.50 4.62 4.71 2.45 2.96 3.03 3.18 4.54 4.62 4.71 4.89 Notes 7. Always greater than 50 mV above VPPOR (PORLEV = 00) for falling supply. 8. Always greater than 50 mV above VPPOR (PORLEV = 01) for falling supply. 9. Always greater than 50 mV above VLVD0. 10. Always greater than 50 mV above VLVD3. Document Number: 001-46931 Rev. *B Page 18 of 32 [+] Feedback CY8CTST110 DC Programming Specifications Table 18 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C. These are for design guidance only. Table 18. DC Programming Specifications Symbol Description VddIWRIT Supply Voltage for Flash Write Operations E Min 2.70 - - 2.2 - - - Vdd - 1.0 50,000 1,800,000 10 Typ - 5 - - - - - - - - - Max - 25 0.8 - 0.2 1.5 Vss + 0.75 Vdd - - - Units V mA V V mA mA V V - Notes Supply Current During Programming or Verify VILP Input Low Voltage During Programming or Verify VIHP Input High Voltage During Programming or Verify IILP Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify IIHP Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify VOLV Output Low Voltage During Programming or Verify VOHV Output High Voltage During Programming or Verify FlashENP Flash Endurance (per block) B IDDP Driving internal pull down resistor. Driving internal pull down resistor. Erase/write cycles per block. FlashENT Flash Endurance (total)[11, 11] FlashDR Flash Data Retention - Erase/write cycles. Years Note 11. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information. Document Number: 001-46931 Rev. *B Page 19 of 32 [+] Feedback CY8CTST110 AC Electrical Characteristics AC Chip Level Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C. These are for design guidance only. Table 19. 5V and 3.3V AC Chip Level Specifications Symbol FIMO24 Description Internal Main Oscillator Frequency for 24 MHz Min 23.4 Typ 24 Max 24.6[12, 13, 14] Units MHz FIMO6 Internal Main Oscillator Frequency for 6 MHz 5.75 6 6.35[12, 13, 14] MHz FCPU1 FCPU2 FBLK5 FBLK33 F32K1 Jitter32k Jitter32k TXRST DC24M Step24M Fout48M Jitter24M1 FMAX TRAMP CPU Frequency (5V Nominal) CPU Frequency (3.3V Nominal) Digital PSoC Block Frequency0(5V Nominal) Digital PSoC Block Frequency (3.3V Nominal) Internal Low Speed Oscillator Frequency 32 kHz RMS Period Jitter 32 kHz Peak-to-Peak Period Jitter External Reset Pulse Width 24 MHz Duty Cycle 24 MHz Trim Step Size 48 MHz Output Frequency 24 MHz Peak-to-Peak Period Jitter (IMO) Maximum Frequency of Signal on Row Input or Row Output. Supply Ramp Time 0.93 0.93 0 0 15 - - 10 40 - 46.8 - - 0 24 12 48 24 32 100 1400 - 50 50 48.0 600 - - 24.6[12, 13], 12.3[13, 14] 49.2[12, 13, 15] MHz MHz MHz MHz kHz ns s % kHz MHz ps MHz s Notes Trimmed for 5V or 3.3V operation using factory trim values. See Figure 8 on page 12. SLIMO mode = 0. Trimmed for 5V or 3.3V operation using factory trim values. See Figure 8 on page 12. SLIMO mode = 1. 24 MHz only for SLIMO mode = 0. Refer to the AC digital block specifications. 24.6[13, 15] 64 200 - - 60 - 49.2[12, 14] Trimmed. Using factory trim values. 12.3 - Notes 12. 4.75V < Vdd < 5.25V. 13. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. 14. 3.0V < Vdd < 3.6V. See Application Note AN2012 "Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation" for information on trimming for operation at 3.3V. 15. See the individual user module data sheets for information on maximum frequencies for user modules. Document Number: 001-46931 Rev. *B Page 20 of 32 [+] Feedback CY8CTST110 Table 20. 2.7V AC Chip-Level Specifications Symbol FIMO12 Description Internal Main Oscillator Frequency for 12 MHz Min 11.5 Typ 120 Max 12.7[16, 17, 18] Units MHz FIMO6 Internal Main Oscillator Frequency for 6 MHz 5.75 6 6.35[16, 17, 18] MHz FCPU1 FBLK27 F32K1 Jitter32k Jitter32k TXRST FMAX TRAMP CPU Frequency (2.7V Nominal) Digital PSoC Block Frequency (2.7V Nominal) Internal Low Speed Oscillator Frequency 32 kHz RMS Period Jitter 32 kHz Peak-to-Peak Period Jitter External Reset Pulse Width Maximum frequency of signal on row input or row output. Supply Ramp Time 0.093 0 8 - - 10 - 0 3 12 32 150 1400 - - - 3.15[16, 17] 12.5[16, 17, 18] MHz MHz kHz ns s MHz s Notes Trimmed for 2.7V operation using factory trim values. See Figure 8 on page 12. SLIMO mode = 1. Trimmed for 2.7V operation using factory trim values. See Figure 8 on page 12. SLIMO mode = 1. 24 MHz only for SLIMO mode = 0. Refer to the AC digital block specifications. 96 200 - - 12.3 - Figure 8. 24 MHz Period Jitter (IMO) Timing Diagram Jitter24M1 F 24M Figure 9. 32 kHz Period Jitter (ILO) Timing Diagram Jitter32k F 32K1 AC General Purpose IO Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C. These are for design guidance only. Table 21. 5V and 3.3V AC GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF Min 0 3 2 7 7 Typ - - - 27 22 Max 12 18 18 - - Units MHz ns ns ns ns Notes Normal Strong Mode Vdd = 4.5 to 5.25V, 10% to 90% Vdd = 4.5 to 5.25V, 10% to 90% Vdd = 3 to 5.25V, 10% to 90% Vdd = 3 to 5.25V, 10% to 90% Notes 16. 2.4V < Vdd < 3.0V. 17. Accuracy derived from IMO with appropriate trim for Vdd range. 18. See Application Note AN2012 "Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation" for information on maximum frequency. for user modules Document Number: 001-46931 Rev. *B Page 21 of 32 [+] Feedback CY8CTST110 Table 22. 2.7V AC GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF Min 0 6 6 18 18 Typ - - - 40 40 Max 3 50 50 120 120 Units MHz ns ns ns ns Notes Normal Strong Mode Vdd = 2.4 to 3.0V, 10% to 90% Vdd = 2.4 to 3.0V, 10% to 90% Vdd = 2.4 to 3.0V, 10% to 90% Vdd = 2.4 to 3.0V, 10% to 90% Figure 10. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRiseF TRiseS TFallF TFallS AC Operational Amplifier Specifications Table 23 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C. These are for design guidance only. Table 23. AC Operational Amplifier Specifications Symbol TCOMP Description Comparator Mode Response Time, 50 mV Overdrive Min Typ Max 100 200 Units ns ns Notes Vdd 3.0V. 2.4V < Vcc < 3.0V. AC Low Power Comparator Specifications Table 24 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V at 25C. These are for design guidance only. Table 24. AC Low Power Comparator Specifications Symbol TRLPC Description LPC Response Time Min - Typ - Max 50 Units s Notes 50 mV overdrive comparator reference set within VREFLPC. AC Analog Mux Bus Specifications Table 25 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C. These are for design guidance only. Table 25. AC Analog Mux Bus Specifications Symbol FSW Description Switch Rate Min - Typ - Max 3.17 Units MHz Notes Document Number: 001-46931 Rev. *B Page 22 of 32 [+] Feedback CY8CTST110 AC Digital Block Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C. These are for design guidance only. Table 26. 5V and 3.3V AC Digital Block Specifications Function All Functions Timer Description Maximum Block Clocking Frequency (> 4.75V) Maximum Block Clocking Frequency (< 4.75V) Capture Pulse Width Maximum Frequency, No Capture Maximum Frequency, With or Without Capture Counter Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS (PRS Mode) CRCPRS (CRC Mode) SPIM SPIS Maximum Input Clock Frequency 20 50 50 - - - - - - - - - - 49.2 49.2 ns ns ns MHz MHz 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V. 50 [19] Min Typ Max 49.2 24.6 Units MHz MHz ns MHz MHz ns MHz MHz Notes 4.75V < Vdd < 5.25V. 3.0V < Vdd < 4.75V. 4.75V < Vdd < 5.25V. - - - - - - - 49.2 24.6 - 49.2 24.6 - - 50 - - 4.75V < Vdd < 5.25V. Maximum Input Clock Frequency - - 24.6 MHz Maximum Input Clock Frequency Maximum Input Clock Frequency Width of SS_ Negated Between Transmissions - - 50 - - - - - - - - - - - 8.2 4.1 - 24.6 49.2 24.6 49.2 MHz MHz ns MHz MHz MHz MHz Maximum data rate at 4.1 MHz due to 2 x over clocking. Transmitter Maximum Input Clock Frequency Maximum Input Clock Frequency with Vdd 4.75V, 2 Stop Bits Receiver Maximum Input Clock Frequency Maximum Input Clock Frequency with Vdd 4.75V, 2 Stop Bits Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking. Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking. Note 19. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period). Document Number: 001-46931 Rev. *B Page 23 of 32 [+] Feedback CY8CTST110 Table 27. 2.7V AC Digital Block Specifications Function All Functions Timer Counter Description Maximum Block Clocking Frequency Capture Pulse Width Maximum Frequency, With or Without Capture Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS (PRS Mode) CRCPRS (CRC Mode) SPIM SPIS Maximum Input Clock Frequency 20 100 100 - - - - - - - - - - 12.7 12.7 ns ns ns MHz MHz 100[20] - 100 - - - - - - - Min Typ Max 12.7 - 12.7 - 12.7 12.7 Units MHz ns MHz ns MHz MHz Notes 2.4V < Vdd < 3.0V. Maximum Input Clock Frequency - - 12.7 MHz Maximum Input Clock Frequency Maximum Input Clock Frequency Width of SS_ Negated Between Transmissions - - 100 - - - - - - - 6.35 4.1 - 12.7 12.7 MHz MHz ns MHz MHz Maximum data rate at 3.17 MHz due to 2 x over clocking. Transmitter Maximum Input Clock Frequency Receiver Maximum Input Clock Frequency Maximum data rate at 1.59 MHz due to 8 x over clocking. Maximum data rate at 1.59 MHz due to 8 x over clocking. AC External Clock Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C. These are for design guidance only. Table 28. 5V AC External Clock Specifications Symbol FOSCEXT - - - Frequency High Period Low Period Power Up IMO to Switch Description Min 0.093 20.6 20.6 150 Typ - - - - Max 24.6 5300 - - Units MHz ns ns s Note 20. 100 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period). Document Number: 001-46931 Rev. *B Page 24 of 32 [+] Feedback CY8CTST110 Table 29. 3.3V AC External Clock Specifications Symbol FOSCEXT Description Frequency with CPU Clock Divide by 1 Min 0.093 Typ - Max 12.3 Units MHz Notes Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met. FOSCEXT Frequency with CPU Clock Divide by 2 or greater 0.186 - 24.6 MHz - - - High Period with CPU Clock Divide by 1 Low Period with CPU Clock Divide by 1 Power Up IMO to Switch 41.7 41.7 150 - - - 5300 - - ns ns s Table 30. 2.7V AC External Clock Specifications Symbol FOSCEXT Description Frequency with CPU Clock Divide by 1 Min 0.093 Typ - Max 3.080 Units MHz Notes Maximum CPU frequency is 3 MHz at 2.7V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. If the frequency of the external clock is greater than 3 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met. FOSCEXT Frequency with CPU Clock Divide by 2 or Greater 0.186 - 6.35 MHz - - - High Period with CPU Clock Divide by 1 Low Period with CPU Clock Divide by 1 Power Up IMO to Switch 160 160 150 - - - 5300 - - ns ns s Document Number: 001-46931 Rev. *B Page 25 of 32 [+] Feedback CY8CTST110 AC Programming Specifications Table 31 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C. These are for design guidance only. Table 31. AC Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3 TDSCLK2 Description Rise Time of SCLK Fall Time of SCLK Data Setup Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK Min 1 1 40 40 0 - - - - - Typ - - - - - 15 30 - - - Max 20 20 - - 8 - - 45 50 70 Units ns ns ns ns MHz ms ms ns ns ns Notes 3.6 < Vdd 3.0 Vdd 3.6 2.4 Vdd 3.0 AC I2C Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C. These are for design guidance only. Table 32. AC Characteristics of the I2C SDA and SCL Pins for Vdd 3.0V Symbol FSCLI2C THDSTAI2C Description SCL Clock Frequency Hold Time (Repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Setup Time for a Repeated START Condition Data Hold Time Data Setup Time Setup Time for STOP Condition Bus Free Time Between a STOP and START Condition Pulse Width of Spikes are Suppressed by the Input Filter. Standard Mode Min Max 0 100 4.0 - Min 0 0.6 Fast Mode Max 400 - Units kHz s s s s s ns s s ns TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C 4.7 4.0 4.7 0 250 4.0 4.7 - - - - - - - - - 1.3 0.6 0.6 0 100[21] 0.6 1.3 0 - - - - - - - 50 Note 21. A fast-mode I2C-bus device may be used in a standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C-bus specification) before the SCL line is released. Document Number: 001-46931 Rev. *B Page 26 of 32 [+] Feedback CY8CTST110 Table 33. 2.7V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not Supported) Symbol FSCLI2C THDSTAI2C Description SCL Clock Frequency Hold Time (Repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Setup Time for a Repeated START Condition Data Hold Time Data Setup Time Setup Time for STOP Condition Bus Free Time Between a STOP and START Condition Pulse Width of Spikes are Suppressed by the Input Filter. Standard Mode Min Max 0 100 4.0 - Min - - Fast Mode Max - - Units kHz s s s s s ns s s ns TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C 4.7 4.0 4.7 0 250 4.0 4.7 - - - - - - - - - - - - - - - - - - - - - - - - - Figure 11. Definition for Timing for Fast/Standard Mode on the I2C Bus SDA TLOWI2C TSUDATI2C THDSTAI2C TSPI2C TBUFI2C SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C Sr P S Document Number: 001-46931 Rev. *B Page 27 of 32 [+] Feedback CY8CTST110 Packaging Information This section shows the packaging specifications for the CY8CTST110 TrueTouch device along with the thermal impedances for each package. It is important to note that emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/design/MR10161. For information on the preferred dimensions for mounting QFN packages, see the following application note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. Figure 12. 32-Pin Sawn QFN Package 001-30999 *A Document Number: 001-46931 Rev. *B Page 28 of 32 [+] Feedback CY8CTST110 Figure 13. 56-Pin (300-Mil) SSOP 51-85062 *C Thermal Impedances Table 34. Thermal Impedances per Package Package [23] 5x5 mm 0.93 MAX 32 QFN Typical JA [22] 22 oC/W Typical JC 12 oC/W Solder Reflow Peak Temperature Table 35 illustrates the minimum solder reflow peak temperature to achieve good solderability. Table 35. Solder Reflow Peak Temperature Package 32 QFN Minimum Peak Temperature[24] 240 oC Maximum Peak Temperature 260 oC Notes 22. TJ = TA + Power x JA. 23. To achieve the thermal impedance specified for the QFN package, the center thermal pad must be soldered to the PCB ground plane. 24. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 5oC with Sn-Pb or 245 5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. Document Number: 001-46931 Rev. *B Page 29 of 32 [+] Feedback CY8CTST110 Development Tool Selection Software PSoC Designer At the core of the PSoC development software suite is PSoC Designer. Used by thousands of PSoC developers, this robust software is facilitating PSoC designs for half a decade. PSoC Designer is available free of charge at http://www.cypress.com under Design Resources > Software and Drivers. PSoC Programmer PSoC Programmer is flexible enough to be used on the bench in development and is also suitable for factory programming. PSoC Programmer works either as a standalone programming application or operates directly from PSoC Designer or PSoC Express. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free of charge at http://www.cypress.com/psocprogrammer. Hi-Tech C Lite Compiler Hi-Tech C Lite is an ANSI C compiler optimized for PSoC to deliver dense, efficient executable code for a smaller-than-ever footprint. Hi-Tech C Lite is available for download at http://www.cypress.htsoft.com. To install the HI-TECH Lite version, download the complier installation file from HI-TECH and choose the Lite option when prompted for a registration key. The Lite version can be upgraded to the 45-day full featured evaluation version or the PRO version at any time, however the PRO version can only be enabled with a purchased registration key. Hi-Tech C Pro Compiler Hi-Tech C Pro is an optional upgrade to PSoC Designer that offers all the benefits of Hi-Tech C Lite with additional features. Hi-Tech C Pro is available for purchase either at the Cypress Online Store or at http://www.cypress.htsoft.com. Hi-Tech C Pro is recommended for touchscreen applications using the Multi-Touch All-Point CY8CTMA120 device. CY3202-C iMAGEcraft C Compiler CY3202 is the optional upgrade to PSoC Designer that enables the iMAGEcraft C compiler. It is available at the Cypress Online Store. At http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items. CY3207ISSP In-System Serial Programmer (ISSP) The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production programming environment. Note CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes: Evaluation Tools All evaluation tools can be purchased from the Cypress Online Store. CY3210-MiniProg1 The CY3210-MiniProg1 kit allows a user to program PSoC devices through the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC through a provided USB 2.0 cable. The kit includes: MiniProg Programming Unit MiniEval Socket Programming and Evaluation Board 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample PSoC Designer Software CD Getting Started Guide USB 2.0 Cable Device Programmers All device programmers can be purchased from the Cypress Online Store. CY3216 Modular Programmer The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes: Modular Programmer Base 3 Programming Module Cards MiniProg Programming Unit PSoC Designer Software CD Getting Started Guide USB 2.0 Cable CY3207 Programmer Unit PSoC ISSP Software CD 110 ~ 240V Power Supply, Euro-Plug Adapter USB 2.0 Cable Document Number: 001-46931 Rev. *B Page 30 of 32 [+] Feedback CY8CTST110 Accessories (Emulation and Programming) Third Party Tools Several tools are specially designed by the following third party vendors to accompany PSoC devices during development and production. Specific details of each of these tools are found at http://www.cypress.com under Design Resources > Evaluation Boards. Build a PSoC Emulator into Your Board For details on emulating the circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, see application note AN2323 "Debugging - Build a PSoC Emulator into Your Board". Ordering Information Flash (Bytes) SRAM (Bytes) Package 32-Pin (5x5 mm 0.93 MAX) SAWN QFN 32-Pin (5x5 mm 0.93 MAX) SAWN QFN (Tape and Reel) 56-Pin OCD SSOP Ordering Code CY8CTST110-32LTXI CY8CTST110-32LTXIT CY8CTST110-00PVXI Single Touch Enabled Y Y Y Multi-Touch Gesture Enabled N N N Multi-Touch All-Point Enabled N N N X/Y Sensor Inputs Up to 24 Up to 24 Up to 24 8K 8K 8K 512 512 512 Ordering Code Definitions CY 8 C TST xxx-32xx Package Type: Thermal Rating: PX = PDIP Pb-Free C = Commercial SX = SOIC Pb-Free I = Industrial PVX = SSOP Pb-Free E = Extended LFX/LKX = QFN Pb-Free AX = TQFP Pb-Free Pin Count: 32-Pin Part Number Family Code: TST = Touchscreen Single-Touch Device Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress Document Number: 001-46931 Rev. *B Page 31 of 32 [+] Feedback CY8CTST110 Document History Page Document Title: CY8CTST110 TrueTouchTM Single-Touch Touchscreen Controller Document Number: 001-46931 Revision ** *A *B ECN Orig. of Change Submission Date 06/18/08 06/30/08 08/06/08 New data sheet Updated X/Y sensor inputs to 24 and supported screen sizes to 4.6" and below Changed operating voltage range to 2.7V to 5.25V. Added other sections based on PSoC data sheets. Description of Change 2518134 DSO/AESA 2523303 DSO/PYRS 2549257 YOM/PYRS Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb (c) Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-46931 Rev. *B Revised July 28, 2008 Page 32 of 32 TrueTouchTM, PSoC DesignerTM, Programmable System-on-ChipTM, and PSoC ExpressTM are trademarks and PSoC(R) is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback |
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